Embedded Random Access Memories (RAMs) have come to be one of the densest blocks in modern complex devices of which the so-called System-on-Chip (SoC) devices are significant examples. A direct consequence of the high level of integration of these complex devices is a high probability of defects inside these extremely compact on-board data storage subsystems. Redundant structures have therefore become a desired feature for embedded memories to achieve high production yields.
Moreover, to enhance productivity by reducing the time required for testing embedded memory arrays of increasingly large capacities and for establishing the required substitution with redundant resources of memory addresses found faulty, many Built-In Self Repair (BISR) structures have been proposed. For example T. Chen, G. Sunada in “A Self-testing and Self-Repairing Structure for Ultra-large Capacity Memories”, 1992, International Test Conference; Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, J. L. Lewandowski, in “Built In Self Repair for Embedded High Density SRAM”, International Test Conference, 1998, pp. 1112-1119; and A. Benso, S. Chiusano, G. Di Natale, P. Prinetto, in “An on-line BIST RAM Architecture with Self-Repair Capabilities”, 2002, IEEE Transactions on Reliability, Volume 51, pp. 123-128 each discloses a software post-fabrication repair approach. R. J. McPartland, D. J. Loeper, F. P. Higgins, R. Singh, G. MacDonald, G. Komoriya, S. Aymeloglu, M. V. DePaolis, C. W. Leung, in “SRAM Embedded Memory with Low Cost, FLASH EEPROM-Switch-Controlled Redundancy”, 2000, IEEE Custom Integrated Circuits Conference, pp. 287-289; and M. Yamaoka, K. Yangisawa, S. Shukuri, K. Norisue, K. Ishibashi, in “A System LSI Memory Redundancy Technique Using an ie-Flash (inverse-gate-electrode Flash) Programming Circuit”, 2001, Symposium on VLSI Circuits Digest of Technical Papers, pp. 71-72 outline a hardware post-fabrication repair approach.
In the newest fabrication technologies, with extremely reduced spacing, many types of complex cell-interaction faults are frequently occurring rather than and in addition to simple stuck-at faults. Therefore, it has become of importance to exhaustively test a memory to discover and localize such complicated fault mechanisms by using appropriate test patterns.
Most of state-of-the-art SoC designs may have as much as 40 to 80 percent of total chip area dedicated to memory arrays, which can be present in one or more of types such as: FLASH, SRAM, ROM, DRAM, according to the complexity of the technology.
Intuitively, post-fabrication repair of an embedded RAM array may be facilitated if the device includes also at least a nonvolatile memory array, because a failed RAM address identified during a built-in self-test (BIST) session may be eventually stored there. Alternatively, a dedicated ROM array may be integrated for covering the permanent storage needs of a BISR structure.
In general, the testing of embedded RAM memories is carried out by employing a programmable built-in self-test (BIST) circuit capable of generating different test patterns to ensure a flexible trade-off between testing time and test coverage of the array cells. However, these BIST structures, despite their programmability, are necessarily tailored for specific memory array aspect ratios and dimensions.
In other words, if the device includes distinct RAM arrays of different sizes, a dedicated BIST module for each of them is normally required, implying an increased cost and complexity.
There are no BISR architectures capable of producing diagnostic information on the reasons why an embedded memory array having a certain inventory of redundancy structures are not repairable.
On the other hand, the testing done during a silicon qualification of a new device prototype is not only oriented to verify the functionality, but also to identify process weaknesses that are responsible for memory cell faults. In this prototyping context even if a certain embedded memory array is not repairable, the test engineer may be interested to know if the irremediable failure has occurred because the redundancy capacity has been exceeded or because the nonvolatile memory in which the substituted addresses are stored is not working correctly.
When a new device has entered the mass production stage, there can be sudden yield drops. In these cases, it may be important to be able to identify in which type of memory array the failures have started to occur. This can be done by gathering separate information on an increasing number of malfunctions occurring either in an embedded RAM array or in an embedded nonvolatile memory array.
Of course, these investigations may be conducted on the devices through appropriate test programs using special external test set-ups, however these investigations are generally time consuming. Quick means may be desirable for discriminating whether the failures have developed in a relatively low-voltage structure (RAM) definition sequence or in a high-voltage structure definition sequence of the fabrication process.
On another account, during mass production, device testing and memory repair (BISR) procedures based on the realization of dedicated built-in structures, should be as fast as possible for evident reasons of productivity. This desire intuitively contrasts with the desirability of generating discriminating failure information on embedded RAM and ROM arrays.